Embodiments relate to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of simplifying a silicide manufacturing process using a photo resist overhang structure. In a method for manufacturing a general semiconductor integrated circuit, a source-drain diffusing region and a gate electrode of a transistor may be formed and may then be contacted to a metal wiring to electrically connect them to the outside. Sheet resistance of both a shallow source-drain diffusing region and a thin polycrystalline silicon gate formed according to a scale down of a transistor should preferably be reduced to 10 to 20 ohms/m2 or less. However, since the sheet resistance cannot be reduced to the 10 to 20 ohms/m2 or less, utility as an interconnection medium may be reduced.
As a method for solving the problem and improving the interconnection, silicide with a low specific resistance value may be formed on and/or over the silicon of the gate or the source-drain region. The process of forming the silicide may be accomplished by deposition metal silicide. For example, metals such as nickel Ni or cobalt Co may be deposited, and may form a metal silicide by heat process. A self aligned silicide process may be used. Such a process may form the silicide only on an active region, made of silicon and a polysilicon as gate forming material, and may not form it on the remaining insulating material.
Since the region formed with the silicide has relatively low resistance, the process cannot be applied to a region that requires high resistance. Therefore, a non-salicide process, which covers a region where the silicide should not be formed with an insulating film and forms the silicide in other regions, is needed. To this end, an oxide film may be used as a silicide mask.
The process will be described with reference to FIG. 1. First, as shown in FIG. 1, gate electrode 4 may be formed on and/or over a surface of semiconductor substrate 1 and gate spacer 6 may then be formed on a side wall of gate electrode 4. Silicon oxide film 2 may be deposited over the resultant, for example by a chemical vapor deposition (CVD) method, or a similar method. Silicon oxide film 2 may be used as a silicide mask.
Then, referring to FIG. 1B, photo resist coating film 8 may be applied on and/or over an upper portion of the deposited silicon oxide 2, for example by a spin coating method, or a similar method.
Next, referring to FIG. 1C, a patterning to define a silicide region and a non-salicide region may be performed through a photolithography process, for example by an exposure method, a development method, or the like to open only a region to be silicided.
Referring to FIG. 1D, silicon oxide film 2 in the region to be silicided, as shown in FIG. 1E, may be removed through a process such as a reactive ion etching (RIE), or a similar process. At approximately the same time, photo resist coating film 8 in the non-salicide may be removed by a strip.
Referring to FIG. 1F, the non-salicide/silicide may be manufactured through annealing after depositing cobalt Co film 10.
However, the related art silicide process is complicated, which may tend to degrade the yield of semiconductor devices.